Electronic calculator systems of the type wherein all of the main electronic functions are integrated in a single large cell integrated semiconductor chip or in a small number of such chips, are described in the following U.S. Patents, which are assigned the assignee of this invention:
The concepts of these prior applications have made possible vast reductions in the cost of small personal-size calculators. Continuing efforts to reduce the cost of these products include the design of a single chip calculator system for use in large capacity calculators, such as scientific or business calculators. The chip disclosed herein may be utilized in scientific or business calculators for instance, because this chip has provisions for a number of storage registers, in addition to operational registers, as well as sufficient capacity to solve the more complicated mathematical expressions and functions used in scientific and business calculators including, for example, trigonometric and logarithmic relationships.
The present invention is related to an indirect addressing system for an electronic calculator. An entire electronic calculator system, including the indirect addressing system of this invention, is disclosed. The electronic calculator disclosed is a serial, word organized calculator; however, it will be evident that the invention disclosed is not limited to that type of calculator system. Prior art calculator systems provided with direct addressing systems i.e., the branch logic formed only direct branches in that the address inserted into an address register or program counter by the branch logic was derived from instruction word defining a branch statement. Further in the prior art, it was known to utilize conditional branch statements whereby the contents of the address register would be either updated by the branch address or merely sequence through to the next normal incremented address according to a logical condition created in the calculator system. It has been found, however, that greater programming flexibility can be provided if at least two of the bits of the address register are provided according to logic conditions generated on the chip to further increase the number of possible locations to which the address counter may cycle upon decoding and indirect address branch.
It is therefore one object of this invention to provide an electronic calculator or microprocessor system with an indirect branching capability. More specifically, it is an object of this invention to provide at least a portion of a branch address to be inserted into the calculator or microprocessors address register according to logical signals generated. In a further aspect, it is an object of this invention to provide a branch address to the address register based on at least in part an address generated by the calculator or microprocessors arithmetic unit.
The foregoing objects are achieved according to the present invention as now described. In a preferred embodiment of the invention, an indirect addressing system is provided on electronic calculator semiconductor chip, the calculator preferably having an input for receiving numeric data and function commands, an arithmetic unit for preforming arithmetic operations by data received by the input, an address register responsive to the input, an instruction word memory for storing a number of instruction words and addressable in response to an address stored in the address register, instruction word logic for decoding instruction words outputted from the instruction word memory and for controlling the arithmetic unit in response thereto and an indirect addressing system. The indirect addressing system includes an auxiliary register which is responsive to at least a portion of each word of numeric data outputted by system's arithmetic unit. The indirect addressing system is responsive to the decoding of a particular instruction word outputted from the instruction word memory for inserting the address stored in the auxiliary register into at least a portion of the address register in response to decoding of the particular instruction word. The calculator or microprocessor system further preferably includes branch logic responsive to the decoding of other particular instruction words by the instruction word decoder logic for performing conditional and/or unconditional branches whereby the contents of the address register may be modified with at least a portion of the other particular instruction words. Thus the electronic calculator or microprocessor system preferably is capable of indirect addressing whereby the contents of the address register is modified at least in part according to a number generated by the systems arithmetic unit and is further capable of indirect addressing whereby the contents of the address register is modified at least in part according to portions of the branch or unconditional branch instruction words stored in the systems instruction word memory.